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| a FEATURES 60 MSPS Sampling Rate 9.3 Effective Number of Bits at fIN = 10.3 MHz 250 mW Total Power at 60 MSPS Selectable Input Bandwidth of 50 MHz or 130 MHz On-Chip T/H and Voltage Reference Single +5 V Supply Voltage +5 V or +3 V Logic I/O Compatible Input Range and Output Coding Options Available APPLICATIONS Medical Imaging Digital Communications Professional Video Instrumentation Set-Top Box BWSEL +5V +5V 10-Bit, 60 MSPS A/D Converter AD9051 FUNCTIONAL BLOCK DIAGRAM GND IN REFERENCE CIRCUITS OUT AD9051 AINB AIN SUM AMP ENCODE TIMING T/H ADC DECODE LOGIC 10 DAC ADC GENERAL DESCRIPTION The AD9051 is a complete 10-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only +5 V and an encode clock to achieve 60 MSPS sample rates with 10-bit resolution. The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with +5 V/+3 V logic. The two-step architecture used in the AD9051 is optimized to provide the best dynamic performance available while maintaining low power consumption. A +2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on a state-of-the-art BiCMOS process, the AD9051 is packaged in a space saving surface mount package (SSOP) and is specified over the industrial temperature range (-40C to +85C). REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998 AD9051-SPECIFICATIONS unless otherwise noted) Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range 2 Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth (BW SEL +V D/NC)3 BANDGAP REFERENCE Output Voltage (I O @ 200 A) Temperature Coefficient Power Supply Sensitivity Reference Input Current (V IN = 2.50 V) SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate 4 Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (t V)5 Output Propagation Delay (t PD)5 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time ENOBS fIN = 1.20 MHz fIN = 10.3 MHz fIN = 29.0 MHz Signal-to-Noise Ratio (SINAD) fIN = 1.20 MHz fIN = 10.3 MHz fIN = 29.0 MHz Signal-to-Noise Ratio (Without Harmonics) fIN = 1.20 MHz fIN = 10.3 MHz fIN = 29.0 MHz 2nd Harmonic Distortion fIN = 1.20 MHz fIN = 10.3 MHz fIN = 29.0 MHz 3rd Harmonic Distortion fIN = 1.20 MHz fIN = 10.3 MHz fIN = 29.0 MHz Two-Tone Intermodulation Distortion (IMD) Differential Phase Differential Gain 6 (VD = +5 V, VDD = +3 V; external reference = 2.50 V; ENCODE = 60 MSPS Temp Test Level Min AD9051BRS Typ Max 10 AD9051BRS-2V Min Typ Max 10 0.75 1.50 0.90 0.75 1.50 0.90 GUARANTEED 0.3 3.0 5.5 10 2.0 5.0 6.0 5 50/130 2.5 33 6.2 2.0 Units Bits LSB LSB LSB LSB % FS % FS ppm/C V p-p LSB k pF MHz V ppm/C mV/V A MSPS MSPS ns ps, rms ns ns ns ns ENOB ENOB ENOB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc Degrees % +25C Full +25C Full +25C +25C Full Full +25C +25C +25C +25C +25C Full Full Full Full Full Full +25C +25C Full Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C I V I V I I VI V V I I V V VI V V VI VI IV V V VI VI V V V I V V I V V I V V I V V I V V V V 0.75 1.50 0.90 0.75 1.50 0.90 GUARANTEED 0.3 2.5 5.0 10 1.25 5.0 6.0 5 50/130 2.5 33 6.2 2.0 -14 4.0 26 -14 4.0 26 2.4 2.6 2.4 2.6 25 60 25 60 2.0 2.5 5 4.0 5.5 10 10 9.6 9.3 9.1 58.5 57 55 59 58 56.5 -74 -73 -67 -74 -70 -65 -65 0.1 0.5 10 5.0 2.0 2.5 5 4.0 5.5 10 10 9.6 9.3 9.1 57.5 56 54 59 58 56.5 -68 -64 -60 -69 -65 -60 -65 0.1 0.5 5.0 10 8.93 8.93 55 54 56 56 -60 -58 -60 -60 -2- REV. A AD9051 Parameter ENCODE INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Encode Pulsewidth High (t EH) Encode Pulsewidth Low (t EL) DIGITAL OUTPUTS Logic "1" Voltage (5.0 VDD) Logic "0" Voltage (5.0 VDD) Logic "1" Voltage (3.0 VDD) Logic "0" Voltage (3.0 VDD) Output Coding7 POWER SUPPLY VD, VDD Supply Current Power Dissipation8 Power Supply Rejection Ratio (PSRR)9 Temp Full Full Full Full +25C +25C +25C Full Full Full Full Test Level VI VI VI VI V IV IV VI VI VI VI Min 2.0 0.8 1 1 7.5 7.5 7.5 4.95 0.05 2.95 0.05 Offset Binary Full Full +25C VI VI I 50 250 2 63 315 10 Offset Binary 50 250 7 63 315 15 mA mW mV/V 2.95 0.05 7.5 7.5 4.95 0.05 7.5 AD9051BRS Typ Max AD9051BRS-2V Min Typ Max 2.0 0.8 1 1 Units V V A A pF ns ns V V V V NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 Contact factory or authorized sales agent for information concerning the availability of expanded input voltage range devices. 3 3 dB bandwidth with full-power input signal. 4 Minimum conversion rate at which all data sheet specifications remain stable. 5 tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels 0.5 V and 2.4 V of the digital outputs with V DD = 3.0 V. The output ac load during test is 5 pF. 6 SNR/harmonics tested with an analog input voltage of -0.5 dBfs. All tests performed at 60 MSPS. 7 Contact factory or authorized sales agent for information concerning the availability of alternative output coding and input range devices. 8 Power dissipation is measured under the following conditions: analog input = -FS at 60 MSPS ENCODE. 9 A change in input offset voltage with respect to a change in V D. Specifications subject to change without notice. REV. A -3- AD9051 ABSOLUTE MAXIMUM RATINGS* VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Analog Inputs . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at +25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range. ORDERING GUIDE Model AD9051BRS AD9051BRS-2V AD9051/PCB AD9051-2V/PCB Temperature Range -40C to +85C -40C to +85C +25C +25C Package Description 28-Lead Shrink Small Outline Package (SSOP) 28-Lead Shrink Small Outline Package (SSOP) Package Options RS-28 RS-28 Evaluation Board Evaluation Board Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND) Analog Input 3.126 (3.50)* 2.5 1.874 (1.50)* *(BRS-2V Version) Voltage Level Positive Full Scale + 1 LSB Midscale Negative Full Scale - 1 LSB OR (Out of Range) 1 0 1 Digital Output MSB . . . LSB 1111111111 0111111111 0000000000 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9051 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. A AD9051 PIN FUNCTION DESCRIPTIONS Pin No. 1, 6, 7, 12, 21, 23 2, 8, 11 3 4 5 9 10 13 14 15 16-19 20, 22 24-27 28 Name GND VD VREFOUT VREFIN BWSEL AINB AIN ENCODE OR D9 (MSB) D8-D5 VDD D4-D1 D0 (LSB) Function Ground. Analog +5 V power supply. Internal bandgap voltage reference (nominally +2.5 V). Input to reference amplifier. Voltage reference for ADC is connected here. Bandwidth Select. NC = 130 MHz nominal. +VD = 50 MHz nominal. Complementary analog input pin (Analog input bar). Analog input pin. Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. Out of range signal. Logic "0" when analog input is in nominal range. Logic "1" when analog input is out of nominal range. Most significant bit of ADC output. Digital output bits of ADC. Digital output power supply (only used by digital outputs). Digital output bits of ADC. Least significant bit of ADC output. PIN CONFIGURATION AIN N N+1 N+2 N+3 N+4 N+5 GND 1 VD 2 VREFOUT 3 VREFIN 4 BWSEL 5 GND 6 GND 7 28 D0 (LSB) 27 D1 26 D2 25 D3 24 D4 23 GND tA ENCODE t EH t EL tPD DIGITAL OUTPUTS N-5 N-4 N-3 N-2 N-1 N AD9051 TOP VIEW VD 8 (Not to Scale) 21 GND 20 VDD AINB 9 AIN 10 VD 11 GND 12 ENCODE 13 OR 14 19 D5 18 D6 17 D7 16 D8 15 D9 (MSB) 22 VDD Figure 1. Timing Diagram VD VD 12k AINB (PIN 9) AIN (PIN 10) 12k 12k INPUT BUFFER ENCODE (PIN 13) 12k Analog Input VDD (PINS 20, 22) +3V TO +5V VD Encode D0-D9, OR VREFOUT (PIN 3) Output Stage Figure 2. Equivalent Circuits VREF REV. A -5- AD9051-Typical Performance Characteristics 255 250 -1 0 245 DISSIPATION - mW BWSEL DISABLED 240 235 230 225 220 ADC GAIN - dB -2 -3 BWSEL ENABLED -4 -5 215 210 -6 1 40 52 80 118 141 ANALOG INPUT FREQUENCY - MHz 201 1 5 15 20 25 30 35 40 45 CLOCK RATE - MSPS 50 55 60 Figure 3. Power Dissipation vs. Clock Rate Figure 6. ADC Gain vs. AIN Frequency 60 59 SNR @ 40MSPS 58 59 AIN = 10.3MHz 58.5 ENCODE = 40MSPS 58 57 SNR/SINAD - dB SINAD @ 40MSPS SNR - dB 56 55 SINAD @ 60MSPS 54 53 52 51 50 0 10 20 30 40 50 60 FREQUENCY - MHz 70 80 90 55.5 55 -40 SNR @ 60MSPS 56 57.5 ENCODE = 60MSPS 57 56.5 -20 0 25 45 TEMPERATURE - C 65 85 Figure 4. SNR/SINAD vs. AIN Frequency Figure 7. SNR vs. Temperature -50 -55 -60 -65 SNR - dB -70 dB 2ND @ 40MSPS -75 -80 -85 -90 -95 -100 0 10 20 30 40 50 60 FREQUENCY - MHz 70 80 90 3RD @ 60MSPS 2ND @ 60MSPS 3RD @ 40MSPS 60 AIN = 10.3MHz 59 58 57 56 55 54 53 52 51 50 5 10 20 30 40 ENCODE - MSPS 50 60 70 Figure 5. Harmonics vs. AIN Frequency Figure 8. SNR vs. Clock Rate -6- REV. A AD9051 0 -10 -20 -30 -40 0 AIN = 10.3MHz ENCODE = 40 MSPS SNR = 58.6dB SINAD = 57.69dB -10 -20 -30 -40 AIN = 15.2MHz ENCODE = 60 MSPS SNR = 58.29dB SINAD = 57.23dB dB dB -50 -60 -70 -80 -90 -50 -60 -70 -80 -90 -100 0 2.5 5.0 7.5 10 12.5 FREQUENCY - MHz 15 17.5 20 -100 0 3.8 7.5 11.3 15.0 18.8 FREQUENCY - MHz 22.5 26.3 30 Figure 9. FFT Plot 40 MSPS, 10.3 MHz Figure 12. FFT Plot 60 MSPS, 15.2 MHz 0 -10 -20 -30 -40 0 AIN = 15.2MHz ENCODE = 40 MSPS SNR = 58.47dB SINAD = 57.04dB -10 -20 -30 -40 AIN = 21.7MHz ENCODE = 60 MSPS SNR = 57.76dB SINAD = 56.27dB dB dB -50 -60 -70 -80 -90 -50 -60 -70 -80 -90 -100 0 2.5 5.0 7.5 10 12.5 FREQUENCY - MHz 15 17.5 20 -100 0 3.8 7.5 11.3 15.0 18.8 FREQUENCY - MHz 22.5 26.3 30 Figure 10. FFT Plot 40 MSPS, 15.2 MHz Figure 13. FFT Plot 60 MSPS, 21.7 MHz 0 -10 -20 -30 -40 0 AIN = 10.3MHz ENCODE = 60 MSPS SNR = 58.15dB SINAD = 57.25dB -10 -20 -30 -40 AIN1 = 9.5MHz, -7dBFS AIN2 = 9.9MHz, -7dBFS IMD = -65dBc ENCODE = 60 MSPS dB dB 0 3.8 7.5 11.3 15.0 18.8 FREQUENCY - MHz 22.5 26.3 30 -50 -60 -70 -80 -90 -50 -60 -70 -80 -90 -100 -100 0 3.8 7.5 11.3 15.0 18.8 FREQUENCY - MHz 22.5 26.3 30 Figure 11. FFT Plot 60 MSPS, 10.3 MHz Figure 14. Two-Tone IMD REV. A -7- AD9051 1.2 6.5 1.0 3V RISING 6 % GAIN ERROR 0.8 5.5 tPD - ns 5V FALLING 0.6 5 3V FALLING 5V RISING 0.4 0.2 4.5 0 0 10 20 30 40 ENCODE - MSPS 50 60 4 -40 -20 0 25 45 TEMPERATURE - C 65 85 Figure 15. Gain vs. Clock Rate Figure 18. tPD vs. Temperature +3 V/+5 V 16 14 12 2.51 2.50 2.49 2.48 REF VOLTAGE OFFSET - mV 10 8 6 4 2 0 2.47 2.46 2.45 2.44 2.43 2.42 VOUT 0 10 20 30 40 ENCODE - MSPS 50 60 0.1 0.25 0.4 0.55 0.7 0.85 1 1.15 1.3 1.45 1.6 1.75 1.9 2.0 SOURCE CURRENT - mA Figure 16. Offset vs. Clock Rate Figure 19. Reference Load Regulation 60 58 56 SNR @ 40MSPS 54 % OCCURANCE 70 75 SNR @ 60MSPS SNR - dB 52 50 48 46 80 70 60 50 40 30 20 44 42 40 25 30 35 40 55 45 50 DUTY CYCLE - % 60 65 10 0 512 513 514 515 CODE 516 517 518 Figure 17. SNR vs. Duty Cycle Figure 20. Midscale Histogram (Inputs Tied) -8- REV. A AD9051 THEORY OF OPERATION 140 +5V 140 VIN -0.625V TO +0.625V 0.1 F +5V 1k 1k 10 Refer to the block diagram on the front page. The AD9051 employs a subranging architecture with digital error correction. This combination of design techniques ensures true 10-bit accuracy at the digital outputs of the converter. At the input, the analog signal is buffered by a high speed differential buffer and applied to a track-and-hold (T/H) that holds the analog value present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse. The two stage architecture completes a coarse and then a fine conversion of the T/H output signal. Error correction and decode logic correct and align data from the two conversions and present the result as a 10-bit parallel digital word. Output data are strobed on the rising edge of the ENCODE command. The subranging architecture results in five pipeline delays for the output data. Refer to the AD9051 Timing Diagram. USING THE AD9051 3 V System +5V AD9631 9 AD9051 AD820 0.1 F Figure 21. Single Supply, Single-Ended, DC-Coupled AD9051 140 +5V 140 VIN -0.625V TO +0.625V -5V 0.1 F 10 +5V AD9631 0.1 F 9 AD9051 The digital input and outputs of the AD9051 can be easily configured to directly interface to 3 V logic systems. The encode input (Pin 13) is TTL compatible with a logic threshold of 1.5 V. This input is actually a CMOS stage (refer to Equivalent Encode Input Stage) with a TTL threshold, allowing operation with TTL, CMOS and 3 V CMOS logic families. Using 3 V CMOS logic allows the user to drive the encode directly without the need to translate to +5 V. This saves the user power and board space. As with all high speed data converters, the clock signal must be clean and jitter free to prevent the degradation of dynamic performance. The AD9051 outputs can also directly interface to 3 V logic systems. The digital outputs are standard CMOS stages (refer to AD9051 Output Stage) with isolated supply pins (Pins 20, 22 VDD). By varying the voltage on the VDD pins, the digital output levels vary respectively. By connecting Pins 20 and 22 to the 3 V logic supply, the AD9051 will supply 3 V output levels. Care should be taken to filter and isolate the output supply of the AD9051 as noise could be coupled into the ADC, limiting performance. Analog Input Figure 22. Single-Ended, Capacitively-Coupled AD9051 140 +5V 140 VIN -0.625V TO +0.625V 0.1 F T1-1T 10 +5V AD9631 -5V 50 9 AD9051 Figure 23. Differentially Driven AD9051 Using Transformer Coupling The AD830 provides a unique method of providing dc level shift for the analog input. Using the AD830 allows a great deal of flexibility for adjusting offset and gain. Figure 24 shows the AD830 configured to drive the AD9051. The offset is provided by the internal biasing of the AD9051 differential input (Pin 9). For more information regarding the AD830, see the AD830 data sheet. +15V 1 2 3 AD830 4 -5V +5V 7 10 The analog input of the AD9051 is a differential input buffer (refer to AD9051 Equivalent Analog Input). The differential inputs are internally biased at +2.5 V, obviating the need for external biasing. Excellent performance is achieved whether the analog inputs are driven single-endedly or differentially (for best dynamic performance, impedances at AIN and AINB should match). Figure 21 shows typical connections for the analog inputs when using the AD9051 in a dc coupled system with single-ended signals. All components are powered from a single +5 V supply. The AD820 is used to offset the ground referenced input signal to the level required by the AD9051. AC coupling of the analog inputs of the AD9051 is easily accomplished. Figure 22 shows capacitive coupling of a single-ended signal while Figure 23 shows transformer coupling differentially into the AD9051. VIN -0.625V TO +0.625V AD9051 9 0.1 F Figure 24. Level-Shifting with the AD830 REV. A -9- AD9051 Overdrive of the Analog Input Special care was taken in the design of the analog input section of the AD9051 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +1.875 V to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range comparators detect when the analog input signal is out of this range and the input buffer is clamped. The digital outputs are locked at their maximum or minimum value (i.e., all "0" or all "1"). This precludes the digital outputs changing to an invalid value when the analog input is out of range. The input is protected to one volt outside the power supply rails. For nominal power (+5 V and ground), the analog input will not be damaged with signals from +5.5 V to -0.5 V. Timing The input range can be adjusted by varying the reference voltage applied to the AD9051. No appreciable degradation in performance occurs when the reference is adjusted 5%. The full-scale range of the ADC tracks reference voltage changes linearly. EVALUATION BOARD The AD9051 evaluation board is a convenient and easy way to evaluate the performance of the AD9051. Analog Input The performance of the AD9051 is very insensitive to the duty cycle of the clock. Pulsewidth variations of as much as 15% for encode rates of 40 MSPS and 10% for encode rates of 60 MSPS will cause no degradation in performance. (See Figure 17, SNR vs. Duty Cycle.) The AD9051 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (refer to Figure 1, Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9051; these transients can detract from the converter's dynamic performance. Power Dissipation The evaluation board requires a 1.25 V p-p input. The signal is buffered by an AD9631 op amp in the unity gain configuration. The signal is then ac coupled before entering the AD9051 where a dc offset is internally generated. Leave E3 unconnected to E4 for usage with the AD9631. To evaluate performance without this buffer, remove the AD9631 and connect E3 to E4. Keep E1 connected to E2 for use in the low bandwidth mode (50 MHz). Removing this connector will enable high bandwidth mode (130 MHz). Low bandwidth is the recommended mode of operation in order to minimize any high frequency noise coupling into the input of the AD9051. Encode The evaluation board is driven with a TTL or CMOS clock into a clock buffer of ac type CMOS logic. This buffer will drive the encode to the AD9051, the data latches, and a "data ready." Data Out The power dissipation specification in the parameter table is measured under the following conditions: encode is 60 MSPS, analog input is -FS. As shown in Figure 3, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS-type devices. The loading determines the power dissipated in the output stages. The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages, but is not realistic from a usage standpoint. The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to Using the AD9051, 3 V System). The lower output swings minimize power consumption as follows: (1/2 CLOAD x VDD2 x Update Rate). Voltage Reference The digital data is captured by a pair 74ACQ574 latches. Any unused connector pins should be grounded to the device that is capturing data from the evaluation board. This minimizes any grounding loops that may degrade performance. A separate power plane is provided for supplying the latches, clock buffer, and digital outputs of the AD9051. This supply can be 3 V or 5 V. Layout The AD9051 is not layout sensitive if some important guidelines are met. The evaluation board layout provides an example where these guidelines have been followed to optimize performance. * Provide a solid ground plane connecting both analog and digital sections. Cuts in this plane near the AD9051 should be kept to a minimum. * Excellent bypassing is essential. All capacitors should be placed as close as possible to the AD9051. No vias should be used to connect capacitors to the AD9051 as this may create a parasitic inductance that can reduce bypassing effectiveness. The AD9051 evaluation board is provided as a design example for customers of Analog Devices. ADI makes no warranties express, statutory, or implied regarding merchantability of fitness for a particular purpose. A stable and accurate +2.5 V voltage reference is built into the AD9051 (Pin 3, VREFOUT). In normal operation the internal reference is used by strapping together Pins 3 and 4 of the AD9051. The internal reference has 500 A of extra drive current that can be used for other circuits. Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9051, which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used to connect to Pin 4 of the AD9051. The VREFIN requires 2 A of drive current. -10- REV. A AD9051 Figure 25. Evaluation Board Top Layer Figure 27. Evaluation Board Bottom Layer Figure 26. Evaluation Board Ground Layer Figure 28. Silkscreen REV. A -11- AD9051 +5VA -5V VDD GND C17 0.1 F C12 1F C10 0.1 F C11 0.1 F C14 1F C13 0.1 F C15 1F VDD AD9051 GND GND P6 1 +5VA GND -5V GND VDD 2 3 4 5 1 2 3 4 5 +5VA GND GND E3 E4 R3 140 R4 140 J1 R5 50 R2 25 C6 0.1 F R1 25 C5 0.1 F +5VA E2 E1 5 6 7 8 9 74ACQ574 1 2 3 4 5 6 7 8 9 10 GND VDD C9 0.1 F GND VDD 1 2 3 4 5 6 7 8 9 10 VDD OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 GND VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK 20 19 17 16 15 14 13 12 11 GND 1 2 3 4 5 6 7 GND C16 0.1 F 8 9 10 11 12 20 19 18 17 16 15 14 13 12 11 GND GND 13 14 15 16 17 18 19 20 21 22 23 24 25 P1 +5VA C2 0.1 F 2 3 4 +5VA1 VREFOUT VREFIN BWSEL D1 27 D2 26 D3 25 D4 24 GND5 23 VDD1 22 GND6 21 VDD2 20 D5 19 GND D6 18 D7 17 D8 16 U4 U1 GND2 GND3 +5A2 AINB C8 0.1 F C3 0.1 F 10 AIN 74ACQ574 OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 GND VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK 2 3 +5VA GND U2 6 C7 0.1 F 11 +5A3 12 GND4 13 ENCODE AD9631 1 2 J1 R6 50 U3 3 14 OR U5 (MSB) D9 15 74AC00 4 5 U3 6 74AC00 9 VDD 10 U3 8 74AC00 12 13 U3 11 74AC00 Figure 29. Evaluation Board Schematic OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead SSOP (RS-28) PRINTED IN U.S.A. 0.03 (0.762) 0.022 (0.558) 0.407 (10.34) 0.397 (10.08) 28 15 0.311 (7.9) 0.301 (7.64) 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.79) 0.066 (1.67) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 8 0.015 (0.38) 0 SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) 0.212 (5.38) 0.205 (5.21) -12- REV. A C3321a-0-11/98 C1 0.1 F 1 GND1 (LSB) D0 28 18 |
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